Bit-serial architecture

In computer architecture, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires.

All digital computers built before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers.

Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.[1]

The HP Nut processor used in many Hewlett-Packard calculators operated bit-serially.[2]

Often, N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.[3]

See also

References
  1. Denyer, Peter B.; Renshaw, David (1985). VLSI signal processing: a bit-serial approach. VLSI systems series. Addison-Wesley. ISBN 978-0-201-13306-6.
  2. Smith, Eric L. "brouhaha" (2023-08-09). "HP-15C CE woes: 1 bug, 2 limitations, 3 questions". MoHPC - The Museum of HP Calculators. Archived from the original on 2023-08-10. Retrieved 2023-09-24.
  3. Andraka., Raymond J. "Building a High Performance Bit Serial Processor in an FPGA" (PDF).
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