Heterogeneous computing

Heterogeneous computing refers to systems that use more than one kind of processor or core. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.[1]

Heterogeneity

Usually heterogeneity in the context of computing refers to different instruction-set architectures (ISA), where the main processor has one and other processors have another - usually a very different - architecture (maybe more than one), not just a different microarchitecture (floating point number processing is a special case of this - not usually referred to as heterogeneous).

In the past heterogeneous computing meant different ISAs had to be handled differently, while in a modern example, Heterogeneous System Architecture (HSA) systems[2] eliminate the difference (for the user) while using multiple processor types (typically CPUs and GPUs), usually on the same integrated circuit, to provide the best of both worlds: general GPU processing (apart from the GPU's well-known 3D graphics rendering capabilities, it can also perform mathematically intensive computations on very large data-sets), while CPUs can run the operating system and perform traditional serial tasks.

The level of heterogeneity in modern computing systems is gradually increasing as further scaling of fabrication technologies allows for formerly discrete components to become integrated parts of a system-on-chip, or SoC. For example, many new processors now include built-in logic for interfacing with other devices (SATA, PCI, Ethernet, USB, RFID, radios, UARTs, and memory controllers), as well as programmable functional units and hardware accelerators (GPUs, cryptography co-processors, programmable network processors, A/V encoders/decoders, etc.).

Recent findings show that a heterogeneous-ISA chip multiprocessor that exploits diversity offered by multiple ISAs can outperform the best same-ISA homogeneous architecture by as much as 21% with 23% energy savings and a reduction of 32% in Energy Delay Product (EDP).[3] AMD's 2014 announcement on its pin-compatible ARM and x86 SoCs, codename Project Skybridge,[4] suggested a heterogeneous-ISA (ARM+x86) chip multiprocessor in the making.

Heterogeneous CPU topology

A system with heterogeneous CPU topology is a system where the same ISA is used, but the cores themselves are different in speed.[5] The setup is more similar to a symmetric multiprocessor. (Although such systems are technically asymmetric multiprocessors, the cores do not differ in roles or device access.) There are typically two types of cores: a higher performance core usually known as the "big" or P-core and a more power efficient core usually known as the "small" or E-core. The terms P- and E-cores are usually used in relation to Intel's implementation of hetereogeneous computing, while the terms big and little cores are usually used in relation to the ARM architecture.

A common use of such topology is to provide better power efficiency, especially in mobile SoCs.

  • ARM big.LITTLE (succeeded by DynamIQ) is the prototypical case, where faster high-power cores are combined with slower low-power cores.[6]
  • Apple has produced Apple silicon SoCs with similar organization.
  • Intel has also produced hybrid x86-64 chips codenamed Lakefield, although not without major limitations in instruction set support. The newer Alder Lake reduces the sacrifice by adding more instruction set support to the "small" core.

Challenges

Heterogeneous computing systems present new challenges not found in typical homogeneous systems.[7] The presence of multiple processing elements raises all of the issues involved with homogeneous parallel processing systems, while the level of heterogeneity in the system can introduce non-uniformity in system development, programming practices, and overall system capability. Areas of heterogeneity can include:[8]

ISA or instruction-set architecture
Compute elements may have different instruction set architectures, leading to binary incompatibility.
ABI or application binary interface
Compute elements may interpret memory in different ways.[9] This may include both endianness, calling convention, and memory layout, and depends on both the architecture and compiler being used.
API or application programming interface
Library and OS services may not be uniformly available to all compute elements.[10]
Low-Level Implementation of Language Features
Language features such as functions and threads are often implemented using function pointers, a mechanism which requires additional translation or abstraction when used in heterogeneous environments.
Memory Interface and Hierarchy
Compute elements may have different cache structures, cache coherency protocols, and memory access may be uniform or non-uniform memory access (NUMA). Differences can also be found in the ability to read arbitrary data lengths as some processors/units can only perform byte-, word-, or burst accesses.[11]
Interconnect
Compute elements may have differing types of interconnect aside from basic memory/bus interfaces. This may include dedicated network interfaces, Direct memory access (DMA) devices, mailboxes, FIFOs, and scratchpad memories, etc. Furthermore, certain portions of a heterogeneous system may be cache-coherent, whereas others may require explicit software-involvement for maintaining consistency and coherency.
Performance
A heterogeneous system may have CPUs that are identical in terms of architecture, but have underlying micro-architectural differences that lead to various levels of performance and power consumption. Asymmetries in capabilities paired with opaque programming models and operating system abstractions can sometimes lead to performance predictability problems, especially with mixed workloads.
Development tools
Different types of processors would typically require different tools (editors, compilers, ...) for software developers, which introduces complexity when partitioning the application across those.[12]
Data Partitioning
While partitioning data on homogeneous platforms is often trivial, it has been shown that for the general heterogeneous case, the problem is NP-Complete.[13] For small numbers of partitions, optimal partitionings that perfectly balance load and minimize communication volume have been shown to exist. [14]

Example hardware

Heterogeneous computing hardware can be found in every domain of computing—from high-end servers and high-performance computing machines all the way down to low-power embedded devices including mobile phones and tablets.

See also

References
  1. Shan, Amar (2006). Heterogeneous Processing: a Strategy for Augmenting Moore's Law. Linux Journal.
  2. "Hetergeneous System Architecture (HSA) Foundation". Archived from the original on 2014-04-23. Retrieved 2014-11-01.
  3. Venkat, Ashish; Tullsen, Dean M. (2014). Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. Proceedings of the 41st Annual International Symposium on Computer Architecture.
  4. Anand Lal Shimpi (2014-05-05). "AMD Announces Project SkyBridge: Pin-Compatible ARM and x86 SoCs in 2015, Android Support". AnandTech. Retrieved 2017-06-11. Next year, AMD will release a low-power 20nm Cortex A57 based SoC with integrated Graphics Core Next GPU.
  5. "Energy Aware Scheduling". The Linux Kernel documentation.
  6. A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors, ACM Computing Surveys, 2015.
  7. Kunzman, D.M. (2011). Programming Heterogeneous Systems. International Symposium on Parallel and Distributed Processing Workshops. doi:10.1109/IPDPS.2011.377.
  8. Flachs, Brian (2009). Bringing Heterogeneous Processors Into The Mainstream (PDF). Symposium on Application Accelerators in High-Performance Computing (SAAHPC).
  9. "Cost-aware multimedia data allocation for heterogeneous memory using genetic algorithm in cloud computing" (PDF). IEEE. 2016. {{cite journal}}: Cite journal requires |journal= (help)
  10. Agron, Jason; Andrews, David (2009). Hardware Microkernels for Heterogeneous Manycore Systems. Parallel Processing Workshops, 2009. International Conference on Parallel Processing (ICPPW). doi:10.1109/ICPPW.2009.21.
  11. Lang, Johannes (2020). Heterogenes Rechnen mit ARM und DSP Multiprozessor-Ein-Chip-Systemen (MSc.). Fachhochschule Vorarlberg. doi:10.25924/opus-4525.
  12. Wong, William G. (30 September 2002). "Tools Matter In Mixed-Processor Software Development". www.electronicdesign.com. Retrieved 2023-08-09.
  13. Beaumont, Olivier; Boudet, Vincent; Rastello, Fabrice; Robert, Yves (August 2002). "Partitioning a square into rectangles: NP-completeness and approximation algorithms" (PDF). Algorithmica. 34 (3): 217–239. CiteSeerX 10.1.1.3.4967. doi:10.1007/s00453-002-0962-9. S2CID 9729067.
  14. Beaumont, Olivier; Becker, Brett; DeFlumere, Ashley; Eyraud-Dubois, Lionel; Lastovetsky, Alexey (July 2018). "Recent Advances in Matrix Partitioning for Parallel Computing on Heterogeneous Platforms" (PDF). IEEE Transactions on Parallel and Distributed Computing.
  15. Gschwind, Michael (2005). A novel SIMD architecture for the Cell heterogeneous chip-multiprocessor (PDF). Hot Chips: A Symposium on High Performance Chips. Archived from the original (PDF) on 2020-06-18. Retrieved 2014-10-28.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.