Memory cell (computing)

Intel 1103, a 1970 metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chip.

The invention of the MOSFET (metal–oxide–semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959,[11] enabled the practical use of metal–oxide–semiconductor (MOS) transistors as memory cell storage elements, a function previously served by magnetic cores.[12] The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (PMOS) static random-access memory (SRAM).[13][14]

SRAM typically has six-transistor cells, whereas DRAM (dynamic random-access memory) typically has single-transistor cells.[15][13] In 1965, Toshiba's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors.[16][17] MOS technology is the basis for modern DRAM. In 1966, Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.[18] In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.[19]

The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 Schottky TTL. One year later, it released the first DRAM integrated circuit chip, the Intel 1103, based on MOS technology. By 1972, it beat previous records in semiconductor memory sales.[20] DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.[15][13]

CMOS memory was commercialized by RCA, which launched a 288-bit CMOS SRAM memory chip in 1968.[21] CMOS memory was initially slower than NMOS memory, which was more widely used by computers in the 1970s.[22] In 1978, Hitachi introduced the twin-well CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a 3 µm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computer memory in the 1980s.[22]

The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells.[23] Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure.[24] Both debuted in 1984, when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory.[23]

The floating-gate MOSFET (FGMOS) was invented by Dawon Kahng and Simon Sze at Bell Labs in 1967.[25] They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce reprogrammable ROM (read-only memory).[26] Floating-gate memory cells later became the basis for non-volatile memory (NVM) technologies including EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM) and flash memory.[27]

Flash memory was invented by Fujio Masuoka at Toshiba in 1980.[28][29] Masuoka and his colleagues presented the invention of NOR flash in 1984,[30] and then NAND flash in 1987.[31] Multi-level cell (MLC) flash memory was introduced by NEC, which demonstrated quad-level cells in a 64 Mb flash chip storing 2-bit per cell in 1996.[23] 3D V-NAND, where flash memory cells are stacked vertically using 3D charge trap flash (CTP) technology, was first announced by Toshiba in 2007,[32] and first commercially manufactured by Samsung Electronics in 2013.[33][34]

The storage element of the DRAM memory cell is the capacitor labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The nMOS transistor (3) acts as a gate to allow reading or writing when open or storing when closed.[35]

For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the nMOS transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a parasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.[36]

The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the nMOS transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).[36]

The working principle of SRAM memory cell can be easier to understand if the transistors M1 through M4 are drawn as logic gates. That way it is clear that at its heart, the cell storage is built by using two cross-coupled inverters. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After been inverted twice it will also feedback the same value.[37]

Therefore there are only two stable states that the circuit can be in:

• ${\displaystyle \scriptstyle Q}$ = 0 and   ${\displaystyle \scriptstyle {\overline {Q}}}$ = 1
• ${\displaystyle \scriptstyle Q}$ = 1 and   ${\displaystyle \scriptstyle {\overline {Q}}}$ = 0

To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (${\displaystyle \scriptstyle WL}$), they become conductive and so the ${\displaystyle \scriptstyle Q}$ and  ${\displaystyle \scriptstyle {\overline {Q}}}$  values get transmitted to the bit line (${\displaystyle \scriptstyle BL}$) and to its complement (${\displaystyle \scriptstyle {\overline {BL}}}$).[37] Finally this values get amplified at the end of the bit lines.[37]

The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line (${\displaystyle \scriptstyle BL}$) and the inverted one into its complement (${\displaystyle \scriptstyle {\overline {BL}}}$). Next transistors M5 and M6 are open by driving a logic 1 (voltage high) into the word line (${\displaystyle \scriptstyle WL}$). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:

1. If the value of the loop is the same as the new value driven, there is no change;
2. if the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.[37]

The flip-flop has many different implementations, its storage element is usually a latch consisting of a NAND gate loop or a NOR gate loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using MOSFETs.

A flash memory cell

Floating-gate memory cells, based on floating-gate MOSFETs, are used for most non-volatile memory (NVM) technologies, including EPROM, EEPROM and flash memory.[27] According to R. Bez and A. Pirovano:

A floating-gate memory cell is basically an MOS transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.[27]