TRIAC

Figure 3: Operation in quadrant 1

Figure 4: Equivalent electric circuit for a TRIAC operating in quadrant 1

Quadrant 1 operation occurs when the gate and MT2 are positive with respect to MT1.^{Figure 1}

The mechanism is illustrated in Figure 3. The gate current makes an equivalent NPN transistor switch on, which in turn draws current from the base of an equivalent PNP transistor, turning it on also. Part of the gate current (dotted line) is lost through the ohmic path across the p-silicon, flowing directly into MT1 without passing through the NPN transistor base. In this case, the injection of holes in the p-silicon makes the stacked n, p and n layers beneath MT1 behave like a NPN transistor, which turns on due to the presence of a current in its base. This, in turn, causes the p, n and p layers over MT2 to behave like a PNP transistor, which turns on because its n-type base becomes forward-biased with respect to its emitter (MT2). Thus, the triggering scheme is the same as an SCR. The equivalent circuit is depicted in Figure 4.

However, the structure is different from SCRs. In particular, TRIAC always has a small current flowing directly from the gate to MT1 through the p-silicon without passing through the p-n junction between the base and the emitter of the equivalent NPN transistor. This current is indicated in Figure 3 by a dotted red line and is the reason why a TRIAC needs more gate current to turn on than a comparably rated SCR.[3]

Generally, this quadrant is the most sensitive of the four. This is because it is the only quadrant where gate current is injected directly into the base of one of the main device transistors.[4]

Figure 5: Operation in quadrant 2

Quadrant 2 operation occurs when the gate is negative and MT2 is positive with respect to MT1.^{Figure 1}

Figure 5 shows the triggering process. The turn-on of the device is three-fold and starts when the current from MT1 flows into the gate through the p-n junction under the gate. This switches on a structure composed by an NPN transistor and a PNP transistor, which has the gate as cathode (the turn-on of this structure is indicated by "1" in the figure). As current into the gate increases, the potential of the left side of the p-silicon under the gate rises towards MT1, since the difference in potential between the gate and MT2 tends to lower: this establishes a current between the left side and the right side of the p-silicon (indicated by "2" in the figure), which in turn switches on the NPN transistor under the MT1 terminal and as a consequence also the pnp transistor between MT2 and the right side of the upper p-silicon. So, in the end, the structure which is crossed by the major portion of the current is the same as quadrant-I operation ("3" in Figure 5).[3]

Figure 6: Operation in quadrant 3

Quadrant 3 operation occurs when the gate and MT2 are negative with respect to MT1.^{Figure 1}

The whole process is outlined in Figure 6. The process happens in different steps here too. In the first phase, the pn junction between the MT1 terminal and the gate becomes forward-biased (step 1). As forward-biasing implies the injection of minority carriers in the two layers joining the junction, electrons are injected in the p-layer under the gate. Some of these electrons do not recombine and escape to the underlying n-region (step 2). This in turn lowers the potential of the n-region, acting as the base of a pnp transistor which switches on (turning the transistor on without directly lowering the base potential is called remote gate control). The lower p-layer works as the collector of this PNP transistor and has its voltage heightened: this p-layer also acts as the base of an NPN transistor made up by the last three layers just over the MT2 terminal, which, in turn, gets activated. Therefore, the red arrow labeled with a "3" in Figure 6 shows the final conduction path of the current.[3]

Figure 7: Operation in quadrant 4

Quadrant 4 operation occurs when the gate is positive and MT2 is negative with respect to MT1. ^{Figure 1}

Triggering in this quadrant is similar to triggering in quadrant III. The process uses a remote gate control and is illustrated in Figure 7. As current flows from the p-layer under the gate into the n-layer under MT1, minority carriers in the form of free electrons are injected into the p-region and some of them are collected by the underlying n-p junction and pass into the adjoining n-region without recombining. As in the case of a triggering in quadrant III, this lowers the potential of the n-layer and turns on the PNP transistor formed by the n-layer and the two p-layers next to it. The lower p-layer works as the collector of this PNP transistor and has its voltage heightened: this p-layer also acts as the base of an NPN transistor made up by the last three layers just over the MT2 terminal, which, in turn, gets activated. Therefore, the red arrow labeled with a "3" in Figure 6 shows the final conduction path of the current.[3]

Generally, this quadrant is the least sensitive of the four.[2] In addition, some models of TRIACs (logic level and snubberless types) cannot be triggered in this quadrant but only in the other three.

A TRIAC starts conducting when a current flowing into or out of its gate is sufficient to turn on the relevant junctions in the quadrant of operation. The minimum current able to do this is called gate threshold current and is generally indicated by I_GT. In a typical TRIAC, the gate threshold current is generally a few milliamperes, but one has to take into account also that:

• I_GT depends on the temperature: The higher the temperature, the higher the reverse currents in the blocked junctions. This implies the presence of more free carriers in the gate region, which lowers the gate current needed.
• I_GT depends on the quadrant of operation, because a different quadrant implies a different way of triggering (see here). As a rule, the first quadrant is the most sensitive (i.e. requires the least current to turn on), whereas the fourth quadrant is the least sensitive.
• When turning on from the off state, I_GT depends on the voltage across the two main terminals MT1 and MT2. Higher voltage between MT1 and MT2 cause greater reverse currents in the blocked junctions, thus requiring less gate current to trigger the device (similar to high temperature operation). In datasheets I_GT is generally given for a specified voltage between MT1 and MT2.

When the gate current is discontinued, if the current between the two main terminals is more than what is called the latching current, the device continues to conduct. Latching current is the minimum current that keeps the device internal structure latched in the absence of gate current. The value of this parameter varies with:

• gate current pulse (amplitude, shape and width)
• temperature
• quadrant of operation

In particular, if the pulse width of the gate current is sufficiently large (generally some tens of microseconds), the TRIAC has completed the triggering process when the gate signal is discontinued and the latching current reaches a minimum level called holding current. Holding current is the minimum required current flowing between the two main terminals that keeps the device on after it has achieved commutation in every part of its internal structure.

In datasheets, the latching current is indicated as I_L, while the holding current is indicated as I_H. They are typically in the order of some milliamperes.

A high ${\displaystyle \operatorname {d} v \over \operatorname {d} t}$ between MT2 and MT1 may turn on the TRIAC when it is off. Typical values of critical static dv/dt are in the terms of volts per microsecond.

The turn-on is due to a parasitic capacitive coupling of the gate terminal with the MT2 terminal, which lets currents into the gate in response to a large rate of voltage change at MT2. One way to cope with this limitation is to design a suitable RC or RCL snubber network. In many cases this is sufficient to lower the impedance of the gate towards MT1. By putting a resistor or a small capacitor (or both in parallel) between these two terminals, the capacitive current generated during the transient flows out of the device without activating it. A careful reading of the application notes provided by the manufacturer and testing of the particular device model to design the correct network is in order. Typical values for capacitors and resistors between the gate and MT1 may be up to 100 nF and 10 Ω to 1 kΩ.[5] Normal TRIACs, except for low-power types marketed as sensitive gate,[6] already have such a resistor built in to safeguard against spurious dv/dt triggering. This will mask the gate's supposed diode-type behaviour when testing a TRIAC with a multimeter.

In datasheets, the static dv/dt is usually indicated as ${\displaystyle \left({\frac {\operatorname {d} v}{\operatorname {d} t}}\right)_{s}}$ and, as mentioned before, is in relation to the tendency of a TRIAC to turn on from the off state after a large voltage rate of rise even without applying any current in the gate.

A high rate of rise of the current between MT1 and MT2 (in either direction) when the device is turning on can damage or destroy the TRIAC even if the pulse duration is very short. The reason is that during the commutation, the power dissipation is not uniformly distributed across the device. When switching on, the device starts to conduct current before the conduction finishes to spread across the entire junction. The device typically starts to conduct the current imposed by the external circuitry after some nanoseconds or microseconds but the complete switch on of the whole junction takes a much longer time, so too swift a current rise may cause local hot spots that can permanently damage the TRIAC.

In datasheets, this parameter is usually indicated as ${\displaystyle {\frac {\operatorname {d} i}{\operatorname {d} t}}}$ and is typically in the order of the tens of ampere per microsecond.[2]

The commutating dv/dt rating applies when a TRIAC has been conducting and attempts to turn off with a partially reactive load, such as an inductor. The current and voltage are out of phase, so when the current decreases below the holding value, the TRIAC attempts to turn off, but because of the phase shift between current and voltage, a sudden voltage step takes place between the two main terminals, which turns the device on again.

In datasheets, this parameter is usually indicated as ${\displaystyle \left({\frac {\operatorname {d} v}{\operatorname {d} t}}\right)_{c}}$ and is generally in the order of up to some volts per microsecond.

The reason why commutating dv/dt is less than static dv/dt is that, shortly before the device tries to turn off, there is still some excess minority charge in its internal layers as a result of the previous conduction. When the TRIAC starts to turn off, these charges alter the internal potential of the region near the gate and MT1, so it is easier for the capacitive current due to dv/dt to turn on the device again.

Another important factor during a commutation from on-state to off-state is the di/dt of the current from MT1 to MT2. This is similar to the recovery in standard diodes: the higher the di/dt, the greater the reverse current. Because in the TRIAC there are parasitic resistances, a high reverse current in the p-n junctions inside it can provoke a voltage drop between the gate region and the MT1 region which may make the TRIAC stay turned on.

In a datasheet, the commutating di/dt is usually indicated as ${\displaystyle \left({\frac {\operatorname {d} i}{\operatorname {d} t}}\right)_{c}}$ and is generally in the order of some amperes per microsecond.

The commutating dv/dt is very important when the TRIAC is used to drive a load with a phase shift between current and voltage, such as an inductive load. Suppose one wants to turn the inductor off: when the current goes to zero, if the gate is not fed, the TRIAC attempts to turn off, but this causes a step in the voltage across it due to the aforementioned phase shift. If the commutating dv/dt rating is exceeded, the device will not turn off.