UltraRAM

In 2023 Quinas company formed to further develop Ultraram.[5]

ULTRARAM is a charge-based memory where the logic state is determined by the presence or absence of electrons in an FG (Front Gate). The FG is electrically isolated from the control gate (CG) by Al2O3 dielectric, and from the underlying channel by the InAs/AlSb TBRT heterostructure. The presence of electrons in the FG (defining a logic 0 state) depletes carriers in the underlying n-type InAs channel, reducing its conductance. Thus, the charge state of the FG and, therefore, the logic state of the memory, is read nondestructively by measuring the current through the channel when a voltage is applied between the source (S) and drain (D) contacts. The final component of the memory is the InAs back-gate (BG), which allows voltages to be applied vertically across the gate stack for various operations.

The novelty underpinning the memory is the TBRT (Triple Barrier Resonant Tunneling) structure, which, unlike single layer barriers, can be switched from a highly electrically resistive state to a highly conductive state by the application of just ±2.5 V. This is achieved by careful design of the thicknesses of the AlSb barriers and InAs QW (Quantum Well) layers. When the memory is in the retention state, i.e., when no voltage is applied to the device, the electron ground states in the TBRT QWs are misaligned with each other and are energetically well above the 300 K electron populations of the InAs FG and channel layers. Indeed, nonvolatility is strengthened by the QW ground states residing at an unusually high energy for a resonant-tunneling structure. This is due to a combination of the ultrathin QWs and the extraordinarily low electron effective mass in InAs. In this state, the TBRT provides a large barrier that prevents electron transfer into or out of the FG. However, the application of a suitable bias across the device tilts the conduction band such that the TBRT QW ground states align with occupied electron states in the channel (during the program operation) or the FG (during the erase operation). This allows electrons to move rapidly across the TBRT region in the intended direction by the inherently fast quantum-mechanical process of resonant tunneling. Due to the low voltages required and the low capacitance per unit area of the device compared to DRAM, ultralow logic state switching energies of 10⁻¹⁷ J are predicted for 20 nm feature size ULTRARAM memories, which is two and three orders of magnitude lower than DRAM and flash respectively. However, before this ultralow switching energy can be realized by fabricating nm-scale devices, the fundamental properties of μm-scale devices must first be understood and optimized. ULTRARAM prototype devices grown on GaAs substrates have previously exhibited experiment-limited, not device-limited, nonvolatile retention of 10⁵ s and an endurance of 10⁶ program-erase cycles.[1]

Retention and endurance characteristics. a) Retention data for a 20 μm gate-length cell. b) S-D current difference (∆IS-D) for the >24 h retention plotted on a log scale. c) Endurance data for continuous program-read-erase-read cycling (5 ms pulses) on a second 20 μm gate-length cell. d) Extended endurance to >10⁷ cycles. e) Oscilloscope trace showing the applied gate bias for a section of the pulse train.

A charged FG is defined as logic '0', and the absence of charge as logic '1'. Program and erase cycles, to charge and discharge the FG respectively, use voltage pulses of ≤±2.55 V on the CG.

InAs channel transistors with submicrometer feature sizes and a subthreshold swing of <100 mV/dec have previously been demonstrated.[6] Consequently, due to the threshold voltage window of 350 mV in the devices designed by the Lancaster team, one can expect the 0/1 current contrast of ULTRARAM to improve to three decades with the implementation of a normally-off channel. Such an improvement of the 0/1 contrast through careful modification of the channel will allow memory arrays to be built with a novel high-density RAM architecture.[1]

The ULTRARAM on silicon devices actually outperform previous incarnations of the technology on GaAs compound semiconductor wafers, demonstrating (extrapolated) data storage times of at least 1000 years, fast switching speed (for device size) and program-erase cycling endurance of at least 10 million, which is one hundred to one thousand times better than flash. Professor Manus Hayne of the Department of Physics at Lancaster, who leads the work said, "ULTRARAM on silicon is a huge advance for our research, overcoming very significant materials challenges of large crystalline lattice mismatch, the change from elemental to compound semiconductor and differences in thermal contraction."[2]

On August 11, 2023, it won the "Most Innovative Flash Memory Startup" award at the 17th Flash Memory Summit (FMS 2023). [7]

• Promotion video: https://www.youtube.com/watch?v=iz-sYyfojw4