iCE (FPGA)

The details of a specific FPGA's bitstream format (which defines how the internal elements of the FPGA are connected and interact with each other) are not usually published by FPGA vendors. This means that, generally, an engineer creating a design for an FPGA must use the tools provided by the FPGA's manufacturer.

In December 2015, at 32C3,[30] Project IceStorm, a toolchain consisting of Yosys (Verilog synthesis frontend), Arachne-pnr (place and route and bitstream generation), and icepack (plain text-to-binary bitstream conversion) tools was presented by Claire Wolf, one of the two developers (along with Mathias Lasser) of the toolchain.[31] The toolchain is notable for being one of, if not the only, fully open-source toolchains for FPGA development. At the same December 2015 presentation, Wolf also demonstrated a RISC-V SoC design built using the open-source toolchain and running on an iCE40 HX8K device. As of March 2021, the toolchain supports iCE40 LP/HX 1K/4K/8K and UP devices.[32]

The iCE65 name was used by SiliconBlue Technologies for the devices it designed for a 65 nm process node. Following the acquisition of SiliconBlue in 2011, the name was used by Lattice Semiconductor until the family was discontinued in April 2012.[18]

The iCE65 L series of devices was intended for low-power applications and handheld devices. The series was first announced in mid 2008,[6] and first shipped to volume customers in early 2009.[7]

Information about a larger device in the series, the iCE65L16, was listed on the SiliconBlue website in 2010,[33] but no mention is made in a 2012 revision of the L-series datasheet.[27] It is unclear whether the device was ever produced commercially.

The iCE65 P-series devices were marketed as a higher-performance version of the L-series devices, intended for use in display, memory, and SERDES applications,[34] and were announced in early 2010.[10][11] Three devices were listed as being part of the series but only one device, the lowest-end iCE65P04, was fully specified. The latest datasheet for the family, published in 2011, lists the other two parts but does not give specifications.[35] Whether these other two devices were ever commercially produced is unclear.

Lattice uses the iCE40 name for its iCE-branded devices produced on a 40 nm process node. The company has also used the codename "Los Angeles" in press releases. The iCE40 family was launched in July 2011 with iCE40 LP and HX parts,[16] and was updated in July 2014 with the iCE40 Ultra parts,[21] in February 2015 with the iCE40 UltraLite parts,[22] and in December 2016 with the iCE40 UltraPlus parts.[24]

iCE40 Ultra, UltraLite, and UltraPlus Parts

Family	Device	LEs	RAM	I²C	SPI	DSP	PWM	Max. I/Os
UltraLite	UL640	640	56 kbit	2	—			26
	UL1K	1280	56 kbit	2				26
Ultra	iCE5LP1K	1100	64 kbit	1	1	2		39
	iCE5LP2K	2048	80 kbit	2	2	4		39
	iCE5LP4K	3520	80 kbit	2	2	4		39
UltraPlus	UP3K	2800	1104 kbit	2	2	4		21
	UP5K	5280	1144 kbit	2	2	8		39

The iCE40 Ultra, UltraLite, and UltraPlus devices are intended for applications with especially low limits on available space and power, such as in wearable technology and smart watches.[21] They are offered in chip-scale, BGA, and QFN packages, with dimensions from 1.4×1.4 mm to 7×7 mm. All devices in family integrate one or two I²C hard cores, with Ultra and UltraPlus devices also including hard SPI bus cores and DSP blocks. UltraLite devices are claimed to operate at half the static current draw of Ultra devices (35 μA compared to 71 μA). Most devices in the family also include a PWM controller, intended to be used to drive IR or RGB LEDs.[36]^: 5

Lattice launched the Ultra family in mid 2014,[21] and the UltraLite family in early 2015.[22] In 2015, the UltraLite family won the Elektra Digital Semiconductor Product of the Year award.[23]

In September 2016, the Apple iPhone 7 was released and made use of an iCE5LP4K device.[37]

In December 2016, Lattice launched the UltraPlus family intended for distributed processing and so-called "mobile heterogeneous computing." The devices include a 1 Mbit (4×256 kbit) single-port RAM (compare with dual-ported RAM), additional DSP processing elements, and support for additional interfaces, such as MIPI I3C, D-PHY, and Virtual GPIO.[24][25]

iCE40 LP and LM Parts

Family	Device	LEs	RAM	I²C	SPI	PLLs	Max. I/Os
LP	LP384	384		—			39
	LP640	640	32 kbit				11
	LP1K	1280	64 kbit			1	97
	LP4K	3520	80 kbit			2	180
	LP8K	7680	128 kbit			2	180
LM	LM1K	1100	64 kbit	2	2	1	39
	LM2K	2048	80 kbit	2	2	1	39
	LM4K	3520	80 kbit	2	2	1	39

The iCE40 LP (low power) and LM (low power with hard IP) parts are intended for use in battery-powered devices as hardware accelerators and I/O port expanders, and for use in the same applications as iCE40 Ultra and UltraLite parts. Compared to the Ultra parts, LP and LM parts are available in a wider range of footprints, offer a greater number of resources (I/O pins, embedded RAM, and logic elements), but consume more power.[28]

LP devices differ from the Ultra devices in that they do not include hard IP cores. Instead, any interface logic must be implemented in the FPGA fabric. This is generally less preferable, as so-called "soft cores" are less power-efficient than hard cores, and often are unable to operate at the same frequencies. A soft core also reduces the number of logic cells available to the application. LM devices integrate two I²C and two SPI hard cores, as well as two strobe generators. Most LP and LM devices integrate one or two phase-locked loops.

The families were launched in mid 2011 and entered volume production in mid 2012.[16][19] They won the Elektra Digital Semiconductor Product of the Year award for 2012.[20] In 2015, it was announced that ZTE would use LM devices to provide sensor hub and infrared remote control functionality in its Star 2 smartphone.[38]

The iCE40 HX devices are intended for high-performance applications. Compared to iCE40 LP and Ultra devices, they offer lower maximum propagation delay (7.30 ns versus 9.00–9.36 ns),[26]^{: 3–13, 3–15} and more I/O pins. HX series devices consume significantly more static power and are available only in significantly larger footprints compared to Ultra and LP parts (7×7 mm to 2×2 cm). Similarly to the LP devices, HX parts do not provide hard IP cores, but do provide one or two phase-locked loops. Unlike other iCE40 devices, the HX parts are also available in QFP footprints.[28]

The HX parts were launched in mid 2011 alongside the LP parts,[16] and entered volume production in mid 2012.[19]