OpenPOWER Microwatt

Microwatt is an open source soft processor core originally written in VHDL by Anton Blanchard at IBM, announced at the OpenPOWER Summit NA 2019[2] and published on GitHub in August 2019. It adheres to the Power ISA 3.0 instruction set and can be run on FPGA boards, booting Linux, MicroPython and Zephyr.[3][4][5][6][7][8]

Microwatt
General information
Launched2019-08-29[1]
Designed byIBM, OpenPOWER Foundation
Architecture and classification
ApplicationSoft core
Instruction setPower ISA 3.0
ppc64le
ppc64be
Physical specifications
Cores
  • 1

Design

Microwatt is a tiny 64-bit bi-endian scalar integer processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers and 32x 64-bit floating-point registers. It uses Wishbone for the memory interface.[4]

The initial development was done in a couple of months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit (MMU) and no floating-point unit.[4]

Later additions to the implementation includes JTAG debugger interface, divider instructions, 16 KB instruction and 32 KB data caches, a non-hypervisor-capable MMU, pipelining[4] and floating-point support.[9]

It's designed using VHDL 2008 and the GHDL simulation environment.[3]

Chiselwatt

A sibling project called Chiselwatt is another open processor core implementing the Power ISA 3.0 instruction set, written in the Scala-based Chisel instead of VHDL.[10][11]

Implementations

History

It is the first processor written from scratch using the open Power ISA 3.0, and is released by the OpenPOWER Foundation as a reference design.

The project started as a demo, proof of concept and a reference implementation for the release of the opensource initiative regarding Power ISA 3.0.[15] The goal for Blanchard was to see if he could make it, and as a software developer, taking on a very low level hardware project was a challenge.[2][3]

Microwatt is set to be fabricated in 130 nm by Efabless "Open MPW Shuttle Program" in 2021.[16]

See also

References
  1. Williams, Chris (2019-08-29). "Get your royalty-free soft-core OpenPOWER processor core blueprints here. Extra, extra – read all about it". The Register.
  2. OpenPOWER Summit NA 2019: Day 2 Keynote Demonstration: Anton Blanchard, IBM & Joe DeLaere, Xilinx
  3. "POWER OpenISA and Microwatt introduction" - Anton Blanchard (LCA 2020)
  4. "Microwatt Microarchitecture" - Paul Mackerras (LCA 2020)
  5. Microwatt and the POWER ISA support in Renode
  6. Linux on Microwatt
  7. OpenPOWER opens further
  8. Day 2 keynote and OpenPOWER blows the doors off: Royalty-free, open soft-core (RISC-V sweating gallons)
  9. Microwatt Floats
  10. Chiselwatt's page on Github
  11. Final Draft of the Power ISA EULA Released
  12. Libre-SOC
  13. "Raptor Announces Kestrel Open-Source, Open HDL/Firmware Soft BMC".
  14. Kestrel SoftBMC Project
  15. Big Blue open sources POWER chip instruction set
  16. "Open MPW metadata for Microwatt". Archived from the original on 2021-02-28. Retrieved 2021-03-30.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.