PWRficient

PWRficient is a microprocessor series by P.A. Semi where the PA6T-1682M was the only one that became an actual product.

POWER, PowerPC, and Power ISA architectures
NXP (formerly Freescale and Motorola)
IBM
IBM/Nintendo
Other
Related links
Cancelled in gray, historic in italic

PWRficient processors comply with the 64-bit Power ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip (SoC) designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

Details

The PA6T is the first and only processor core from P.A. Semi, in two distinct product lines: 16xxM dual core and 13xxM/E single core. The PA6T lines differed in L2 cache size, memory controllers, communication functionality, and cryptography offloading features. P.A. Semi planned up to 16 cores.[1]

The PA6T is the first Power ISA core designed from scratch in the previous ten years outside the AIM alliance, which included IBM, Motorola, Freescale, and Apple Inc. Since Texas Instruments was an investors in P.A. Semi, it was suggested that its fabrication plants would have manufactured the PWRficient processors.[1]

PWRficient processors were initially shipped to select customers in February 2007 and were released worldwide in Q4 2007.[2]

P.A. Semi was bought by Apple Inc. in April 2008,[3] and closed development of PWRficient architecture processors. However, it will continue to manufacture, sell, and support these components for the foreseeable future due to an agreement with the US Government for some military applications.[4][5] Some components of the P.A. Semi PWRficient were later integrated into Apple silicon.[6]

Implementation
PA6T-1682M
General information
Launched2007
Discontinued2008
Designed byP.A. Semi
Performance
Max. CPU clock rate1.8 GHz to 2.0 GHz
Cache
L1 cache64+64 KB/core
L2 cache2 MB/core
Architecture and classification
Technology node65 nm
MicroarchitecturePA6T
Instruction setPower ISA (Power ISA v.2.04)
Physical specifications
Cores
  • 2

PWRficient processors comprise three parts:

CPU

PA6T

Memory system

CONEXIUM

  • scalable cross-bar interconnect
  • 1–8 SMP cores
  • 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
  • 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
  • 64 GB/s peak bandwidth
  • MOESI coherency

I/O

ENVOI

Users

References
  1. "PA Semi heads to 16 cores on back of $50m boost". The Register. 2006-05-17. Retrieved 2012-07-02.
  2. "Press release". P.A. Semi. Archived from the original on August 21, 2007. Retrieved 2007-02-07.
  3. Brown, Erika; Corcoran, Elizabeth; Caulfield, Brian (2008-04-23). "Apple Buys Chip Designer". Forbes. Retrieved 2011-07-05.
  4. "Apple will please missile makers by backing PA Semi's chip". The Register. 2008-05-16. Retrieved 2011-07-05.
  5. "DoD may push back on Apple's P.A. Semi bid". EETimes. 2008-05-23. Archived from the original on 2010-12-13. Retrieved 2011-07-05.
  6. "[PATCH v2 00/11] Add Apple M1 support to PASemi i2c driver".
  7. http://pasemi.com/news/pr_2007_12_20a.html
  8. "Mercury Computer Systems and P.A. Semi Collaborate to Bring PWRficient Processor to Signal and Image Processing Applications". June 7, 2007. Retrieved August 18, 2022.
  9. "NEC pops PA Semi chips into storage gear". The Register.
  10. "X1000". Archived from the original on 2011-07-07. Retrieved 2011-07-05.
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