M·CORE

M·CORE is a low-power, RISC-based microcontroller architecture developed by Motorola (subsequently Freescale, now part of NXP), intended for use in embedded systems. Introduced in late 1997, the architecture combines a 32-bit internal data path with 16-bit instructions,[1] and includes a four-stage instruction pipeline. Initial implementations used a 360nm process and ran at 50 MHz.

M·CORE processors[2] employ a von Neumann architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to have low power consumption and high code density.[3]

References

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Reduced instruction set computer (RISC) architectures
Origins	IBM 801 Berkeley RISC Stanford MIPS
Active	Analog Devices Blackfin ARC ARM AVR eSi-RISC LatticeMico8, LatticeMico32 MIPS OpenRISC Power ISA Renesas M32R, SuperH, V850 RISC-V SPARC Sunway Unicore Xilinx MicroBlaze, PicoBlaze
Discontinued	Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CR16 CRISP DEC PRISM Intel i860, i960 META MIPS-X Motorola 88000, M·CORE PA-RISC POWER, PowerPC, ROMP