Blackfin

mounted Blackfin BF526 in an Agilent oscilloscope

What is regarded as the Blackfin "core" is contextually dependent. For some applications, the DSP features are central. Blackfin has two 16-bit hardware MACs, two 40-bit ALUs and accumulators, a 40-bit barrel shifter, and four 8-bit video ALUs; Blackfin+ processors add a 32-bit MAC and 72-bit accumulator. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications use the RISC features, which include memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present. The standard Blackfin assembly language is written using an algebraic syntax: instead of prefix commands used in many other assembly languages.

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space, so that from a programming point of view, the Blackfin has a Von Neumann architecture.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and SRAM. Some Blackfin processors also include mass-storage interfaces such as ATAPI and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which is designed for higher throughput for applications that can use it, such as real-time standard-definition (D1) video encoding and decoding.

The architecture of Blackfin contains the usual CPU, memory, and I/O that is found on microprocessors or microcontrollers. These features enable operating systems.

All Blackfin processors contain a Memory Protection Unit (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support operating systems, RTOSs and kernels like ThreadX, μC/OS-II, or NOMMU Linux. Although the MPU is referred to as a Memory Management Unit (MMU) in the Blackfin documentation, the Blackfin MPU does not provide address translation like a traditional MMU, so it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX.

Blackfin supports three run-time modes: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an exception will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space.

Blackfin uses a variable-length RISC-like instruction set consisting of 16-, 32- and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32- and 64-bit opcodes. This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures.

The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and image compression and decompression algorithms.