NEC V20

The V20's die comprised 63,000 transistors; more than double the 29,000 of the 8088 CPU.[1] The chip was designed for a clock duty cycle of 50%, compared to the 33% duty cycle used by the 8088.[3] The V20 has two, 16-bit wide internal databuses, allowing two data transfers to occur concurrently.[4] Differences like that meant that a V20 could typically complete more instructions in a given time than an Intel 8088 running at the same frequency.[2]

The V20 was fabricated in 2-micron CMOS technology.[5][3] Early versions ran at speeds of 5, 8, and 10 MHz.[6]^: 2 In 1990, an upgrade to the fabrication process technology resulted in the V20H and V20HL, with improved performance and reduced power consumption.[5] Later versions added speeds of 12 and 16 MHz. The V20HLs were also completely static, allowing their clock to be stopped.

The V20 was described as 16-bits wide internally. It used an 8-bit external data bus that was multiplexed onto the same pins as the low byte of the address bus. Its 20-bit wide address bus was able to address 1 MB of memory.

The V20 was reported to have been compatible with the Intel 8087 floating-point unit (FPU) coprocessor.[7] NEC also designed their own FPU, the μPD72091, which was cancelled before reaching production. They followed this with a revised design, the μPD72191, but it is unclear how many, if any, of this second part were produced.[8]

The V30, a nearly identical CPU with a 16-bit wide external data bus, debuted on March 1, 1984.[9][5] It was pin and object-code compatible with the Intel 8086.

Sony CXQ70108D 8 MHz

The V20's ISA includes several instructions not executed by the 8088, with instructions for bit manipulation, packed BCD operations, multiplication, and division. They also include new real-mode instructions from the Intel 80286.[10]

The ADD4S, SUB4S, and CMP4S instructions were able to add, subtract, and compare huge packed binary-coded decimal numbers stored in memory. Instructions ROL4 and ROR4 rotate four-bit nibbles. Another family consisted of the TEST1, SET1, CLR1, and NOT1 instructions, which test, set, clear, and invert single bits of their operands, but are far less efficient than the later i80386 equivalents BT, BTS, BTR, and BTC; neither are their encodings compatible. There were two instructions to extract and insert bit fields of arbitrary lengths (EXT, INS). And finally, there were two additional repeat prefixes, REPC and REPNC, which amended the original REPE and REPNE instructions for scanning a string of bytes or words (with instructions SCAS and CMPS) while a less or not less condition remained true.[11]

The V20 offered a mode that emulated an Intel 8080 CPU. A BRKEM instruction is issued to start 8080 emulation. The operand of the instruction specifies an interrupt number whose vector contains the segment:offset where emulation is to begin. To end, a RETEM instruction is issued in 8080 code. One feature not often employed is the CALLN (call native) which issues an 8086-type interrupt call that enables x86 code (which returns using an IRET) to be mixed in with 8080 code.

Another mode put the processor into a power-saving state via a HALT instruction.[6][7]

In 1982, Intel sued NEC over the latter's μPD8086 and μPD8088. This suit was settled out of court, with NEC agreeing to license the designs from Intel.[12]

In late 1984, Intel again filed suit against NEC, claiming that the microcode in the V20 and V30 infringed its patents for the 8088 and 8086 processors.[13] NEC software engineer Hiroaki Kaneko had studied both the hardware design of the Intel CPUs and the original Intel microcode.

In its ruling, the court determined that the microcode in the control store constitutes a computer program, and so is protected by copyright.[14] They further found Intel to have forfeited their copyright by neglecting to ensure that all second-source chips were suitably marked. The court also determined that NEC did not simply copy Intel's microcode, and that the microcode in the V20 and V30 was sufficiently different from Intel's to not infringe Intel's patents.

The judge in the case accepted NEC's cleanroom evidence. He also approved of NEC's use of reverse engineering with respect to the creation of NEC's Rev.2 microcode, without commenting on it with respect to the Rev.0 code.[14]^{: 212–221}

V20 on a motherboard

NEC V30 (μPD70116), 10 MHz

NEC V40 (μPD70208)

NEC V53A (µPD70236A)

• Die photos
• 
  NEC V30
• 
  NEC V50
• 
  NEC V53

• NEC RX116, dedicated ITRON-1-based 16-bit RTOS
• NEC μPD9002, a Z80 and x86 compatible CPU
• VIA Technologies Alternate Instruction Set, a CPU implementing a similar scheme to enter and exit into an alternate instruction set mode

• V20/V30 User's Manual. NEC. October 1986. Archived from the original (PDF) on 2013-01-08.
• Davis, Randy (December 1985 – January 1986). Written at Greenville, Texas, USA. "The New NEC Microprocessors - 8080, 8086, Or 8088?" (PDF). Micro Cornucopia. No. 27. Bend, Oregon, USA. pp. 4–7. ISSN 0747-587X. Archived (PDF) from the original on 2020-02-11. Retrieved 2020-02-11.

• Buchty, Rainer. "Casiorama". www.buchty.net.
• "NEC V20". cpu-collection.de.
• Hinckley, Robert C. (January 1987). "NEC v. Intel: Will Hardware Be Drawn into the Black Hole of Copyright Editors'". Santa Clara High Technology Law Journal. Vol. 3, no. 1. pp. 23–72.