Low Pin Count

The LPC specification defines seven mandatory signals required for bidirectional data transfer:

• LCLK: 33.3 MHz clock, provided by the host. May be connected to the conventional PCI clock (PCICLK), thereby not requiring a dedicated pin on the host (south bridge).
• LRESET#: Active-low bus reset. May be connected to PCIRST#.
• LFRAME#: This active-low signal indicates the beginning of an LPC bus transaction. Driven by the host only.
• LAD[3:0]: These four bidirectional signals carry multiplexed address, data, and other information. Like the previous two control signals, these signals have weak pull-up resistors on them, so they will remain in the all-ones state if not actively driven by a device.

There are six additional signals defined, which are optional for LPC devices that do not require their functionality, but support for the first two is mandatory for the host:

• LDRQ#: DMA/bus master request. This is an output from a device that wants to perform direct memory access, either via the Intel 8237 compatible DMA controller, or the LPC-specific bus master protocol. The host must provide one corresponding input pin per device that needs it (minimum two).
• SERIRQ: Serialized Intel 8259 compatible interrupt signal.[5] One line is shared by all LPC devices and the host.
• CLKRUN#: Open-collector signal used to restart the clock in systems that can stop it for power management. Not required if the host does not stop the clock. May be connected to the equivalent PCI signal.
• LPME#: Open-collector power management event, to wake the system from a sleep state. Equivalent to the PCI bus PME# signal.
• LPCPD#: Optional output from the host to warn the LPC device that power is about to be removed and it should not make any interrupt or DMA requests.
• LSMI#: System management interrupt request. This is only required if an LPC device needs to trigger an SMI# in response to a bus access (e.g. to perform software emulation of a missing hardware peripheral). Otherwise, the slower SERIRQ protocol can be used to request an SMI.

The LPC bus derives its electrical conventions from those of conventional PCI. In particular, it shares the restriction that two idle cycles are required to "turn around" any bus signal so that a different device is "speaking". In the first, the bus is actively driven high. In the second, the bus is undriven and held high by the pull-up resistors. A new device may begin sending data over the bus on the third cycle. LPC operations spend a large fraction of their time performing such turn-arounds.

As mentioned, the LPC bus is designed to have performance similar to the ISA bus. The exact data transfer rates depend on the type of bus access (I/O, memory, DMA, firmware) performed and by the speed of the host and the LPC device. All bus cycles spend a majority of their time in overhead rather than data transfer - except the 128-byte firmware read cycle, in which 256 of the 273 clock ticks consumed by this cycle actually are used to transfer data to get a throughput of 15.63 MB/s.[6] The next fastest bus cycle, the 32-bit ISA-style DMA write cycle that is defined in this standard, can transfer up to 6.67 MB/s because only 8 out of 20 clock ticks used in this bus cycle actually transfer data while the rest of the cycles are overhead.[6]

One of the slowest bus cycles is a simple memory read or write, where only 2 of the 17 clock ticks (plus any wait states imposed by the device) transfer data, for a transfer rate of 1.96 MB/s.

Intel designed the LPC bus so that the system BIOS image could be stored in a single flash memory chip directly connected to the LPC bus. Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port.[7]

A CPLD or FPGA can implement an LPC host or peripheral.[8]

The original Xbox game console has an LPC debug port that can be used to force the Xbox to boot new code.[9][10]

Memory and I/O accesses are allowed as single-byte accesses only.

For a write, the address described above is followed by the data field, 8 bits transferred with the least significant nibble first over two cycles.

Following this, the host turns the bus over to the device. This turn-around takes two cycles, and operates the same way as the conventional PCI bus control signals: for one cycle, the host drives the LAD lines high (1111). During the second cycle, the host ceases to drive the lines, although they remain high due to the pull-up resistors. The device may drive the lines beginning with the third cycle.

Following any turn-around to the device is a minimum of one SYNC cycle. The number is variable, under the control of the device to add as many wait states as it needs. The bit patterns 0101 and 0110 indicate that the sync cycles will continue. The wait ends when the device drives a pattern of 0000 (ready) or 1010 (error) on the LAD bus for one cycle.

In the case of reads, this is followed by 8 bits of data, transferred least significant nibble first over two cycles, the same as for a write.

The device then turns the bus around to the host again (taking another two cycles), and the transfer is complete; the host may send the START field of another transfer on the next cycle.

If the host attempts a transfer to an unused address, no device will drive the SYNC cycles and the host will see 1111 on the LAD bus. After seeing three cycles of 1111 (two cycles are allowed, in addition to the two turn-around cycles, for a slow device to decode the address and begin driving SYNC patterns), the host will abort the operation.

The Platform Controller Hub (PCH) chip or the southbridge chip acts as the host and controls the LPC bus. It also acts as the central DMA controller for devices on that bus if the memory controller is in the chipset. In CPUs that contain their own memory controller(s), the DMA controller is located in the CPU. For compatibility with software originally written for systems with the ISA bus, the DMA controller contains the circuit equivalents of "legacy" onboard peripherals of the IBM PC/AT architecture, such as the two programmable interrupt controllers, the programmable interval timer, and two ISA DMA controllers, which are all involved in "ISA-style DMA".

ISA-compatible DMA uses an Intel 8237-compatible DMA controller on the host, which keeps track of the location and length of the memory buffer, as well as the direction of the transfer. The device simply requests service from a given DMA channel number, and the host performs a DMA access on the LPC bus.

DMA requests are made using the device's LDRQ# signal. Normally high, a device can indicate a transition on an ISA-compatible DRQ line by sending a 6-bit request: a 0 start bit, the 3-bit DMA channel number (most significant bit first), one bit of new request level (almost always 1, indicating that a DMA transfer is requested), and a final 1 stop bit. The host then performs a DMA cycle. DMA cycles are named based on the memory access, so a "read" is a transfer from memory to the device, and a "write" is a transfer from the device to memory.

The "address" consists of two cycles: a 3-bit channel number and 1-bit terminal count indication (the ISA bus's TC pin, or the 8237's EOP# output), followed by a 2-bit transfer size.

By default, DMA channels 0–3 perform 8-bit transfers, and channel 5–7 perform 16-bit transfers; but an LPC-specific extension allows 1-, 2-, or 4-byte transfers on any channel. When a multi-byte transfer is performed, each byte has its own SYNC field, as described below. DMA transfers allow an additional SYNC field value: a pattern of 1001 indicates that the device is ready with the current byte, and also wishes to transfer more bytes. The standard "ready" pattern of 0000 indicates that this is the last byte.

A normal SYNC "ready" pattern of 0000 (or an error pattern of 1010) requests that the host stop DMA after the immediately following byte until the device makes another DMA request via the LDRQ# signal. A pattern of 1001 indicates that the host should consider he device's DMA request still active; the host will continue with any remaining bytes in this transfer or start another transfer, as appropriate, without a separate request via LDRQ#.

For a DMA write, where data is transferred from the device, the SYNC field is followed by the 8 bits of data and another SYNC field, until the host-specified length for this transfer is reached, or the device stops the transfer. A two-cycle turnaround field completes the transaction. For a DMA read, where data is transferred to the device, the SYNC field is followed by a turnaround, and the data—turnaround—sync—turnaround sequence repeats for each byte transferred.

Serialized interrupts are transmitted over a single shared SERIRQ line with the help of the clock. A time slot is dedicated to each interrupt request, with the initial synchronization being done by the host.[5] As a simplified example:

• The host drives the SERIRQ line low for eight clocks, then high for another, and lets the bus float for a final turnaround cycle.
• If a device needs to request IRQ#6, it waits for 6×3=18 clocks, then drives SERIRQ low for a clock and high for another.

The devices can synchronize at the first step because the line can only be driven low for two or more consecutive clocks by the host: no other device drives it low for more than one clock. The host recognizes the sources of the interrupts by watching the line while counting the number of clocks: if it sees the SERIRQ line being driven low at the eighteenth clock, then IRQ 18/3=6 is asserted.

The above is the continuous mode, where the host initiates the protocol. In the quiet mode, a device requests interruption by driving SERIRQ low for a clock. The host then continues driving the line low for the other seven clocks. From this point on, the protocol is the same. In both modes, the number of clocks of the initial synchronization pulse may range from four to eight.

At the beginning, the protocol works in continuous mode. At the end of each complete bus transaction (after the host has driven SERIRQ low and then waited for all devices to send interrupt requests) the host sends a final message: it drives the SERIRQ line low for two or three clocks depending on the mode that will be used in the next transaction.

The advantage of using serialized interrupts over the traditional mechanism is that only the single SERIRQ line is necessary (apart from the clock, which is present anyway), not a line for each interrupt level.