DEC V-11

The ROM/RAM chip (DC327) implemented one-fifth of the patchable control store. It contained a 16,384 by 8-bit (16 KB) read-only memory (ROM), a 1,024 by 8-bit (1 KB) random-access memory RAM and a 32 by 14-bit content-addressable memory (CAM). The ROM contained the control store, with the RAM used to hold control store patches. The ROM/RAM consisted of 208,000 transistors on a die measuring 344 mils by 285 mils (8.74 mm by 7.24 mm) for an area of 98,040 mil² (63.25 mm²). It dissipated 1 W.

The I/E chip (DC328) contained an instruction buffer, a microsequencer, an execution unit and a mini-translation buffer (MTB). The instruction buffer is a two-entry 32-bit buffer that held prefetched instructions. It improved performance by maintaining a number of instructions ready for execution. The hardware attempted to keep the instruction buffer full at all times. The execution unit consisted of sixteen 32-bit general purpose registers defined by the VAX ISA, an arithmetic logic unit (ALU) and a shifter. The MTB is a translation lookaside buffer (TLB). It contained five page table entries (PTEs), one for instruction and four for data. In the event of a miss, the backup translation buffer (BTB) in the M chip is used. The I/E chip consisted of 60,000 transistors on a die measuring 354 mils by 358 mils (8.99 mm by 9.09 mm) for an area of 126,732 mil² (81.76 mm²). It dissipated 5 W.

The M chip (DC329) was responsible for memory management and interrupt handling. It contained the backup translation buffer (BTB) tags, cache tags and internal processor registers. The M chip also contained the I/O functionality defined by the VAX architecture and generated the clock signal for the chip set.

The backup translation buffer was essentially a translation lookaside buffer (TLB) which handled a miss in the MTB. The BTB contained 512 page table entries (PTEs), of which 256 were for system-space pages and 256 were for process-space pages. There are 128 BTB tags, one for every four PTEs, located in the M chip. The BTB was implemented with external RAMs.

There are 26 internal processor registers, which are used by the microcode for temporary storage when executing complex instructions requiring multiple cycles.

The M chip consisted of 54,000 transistors on a die measuring 339 mil by 332 mil (8.61 mm by 8.43 mm) for an area of 112,548 mil² (72.61 mm²). It dissipated 3 W.

The F chip (DC330) contained a floating-point unit (FPU). It supported most VAX floating-point instructions and the f_floating, d_floating and g_floating data types defined in the VAX architecture and was also responsible for executing integer divide and multiply instructions. The F chip received opcodes from the I/E chip and microinstructions from the control store over the MIB bus. Operands were received from the memory or the general purpose registers over the DAL bus, which is also used to write back results. It consisted of 29,600 transistors on a 341 mil by 288 mil die (8.66 mm by 7.32 mm) for an area of 98,208 mil² (63.36 mm²). It dissipated 2.5 W.

The F chip was a derivative of the FPA, which belonged to the J-11 microprocessor chip set, an implementation of the PDP-11. The F chip was supposed to be a completely new design developed for the V-11, but was cancelled in favor of a derivative as part of an effort to simplify the V-11 so it could be completed quicker as development of the MicroVAX 78032 had begun.

The V-11 has an external 8 KB primary cache. The cache was physically addressed and has a 64-byte cache block.

The V-11 chip set contained a total of 1,183,600 transistors spread over nine dies fabricated in Digital's ZMOS process, a 3.0 µm NMOS process with two levels of interconnect. (The 'Z' in the name was chosen because it looked like a '2' -- having 2 layers of metal was notable.)