Alpha 21364

The development of the Alpha 21364 was most focused on features that would improve memory performance and multiprocessor scalability. The focus on memory performance was the result of a forward-looking article published in Microprocessor Report titled, "It's the Memory, Stupid!" written by Richard L. Sites, who co-led the definition of the Alpha architecture.[5] The article concluded that, "Over the coming decade, memory subsystem design will be the only important design issue for microprocessors."

The Alpha 21364's core is based on the EV68CB, a derivative of the Alpha 21264. The only modification was a larger victim buffer, now quadrupled in capacity to 32 entries. The 32 entries of victim buffer is divided equally into 16 entries each for the Dcache and Scache. Although the Alpha 21364 is a fourth-generation implementation of the Alpha Architecture, aside from this modification, the core is otherwise identical to the EV68CB derivative of the Alpha 21264.[6]

The secondary cache (termed "Scache") is a unified cache with a capacity of 1.75 MB. It is 7-way set associative, uses a 64-byte line size, and has a write-back policy. The cache is protected by single-bit error correction, double-bit error detection (SECDED) error-correcting code (ECC). It is connected to the cache controller by a 128-bit data path. Access to the cache is fully pipelined, yielding a sustainable bandwidth of 16 GB/s at 1.0 GHz.

The time required for data requested from the cache to when it can be used is 12 cycles.[7] The 12-cycle latency was considered by observers, such as the Microprocessor Report, to be significant. The latency of the Scache was not reduced further as it would have not improved performance. The Alpha 21264 core upon which the Alpha 21364 was based on was designed to use an external cache built from commodity SRAM, which has a significantly higher latency than the on-die Scache of the Alpha 21364. Thus, it could only accept data at a limited rate. Once improving latency saw no further gains, the designers focused on reducing the power consumed by the Scache.[8] Compaq was not willing to remedy this deficiency as it would have required the Alpha 21264 core to be modified significantly.[9] The high latency of the Scache permitted the cache tags be looked up first to determine if the Scache contained the requested data and in which bank it was located in before powering up the Scache bank and accessing it. This avoided unproductive Scache accesses, reducing power consumption.

The tag store consisted of 5.75 million transistors and data store of 108 million transistors.[8]

The Alpha 21364 has two integrated memory controllers that support Rambus DRAM (RDRAM) that operate at two thirds of the microprocessor's clock frequency, or 800 MHz at 1.2 GHz. Compaq designed custom memory controllers for the Alpha 21364, giving them capabilities not found in standard RDRAM memory controllers such as having all the 128 pages open, reducing the access latency to those pages; and proprietary fault-tolerant features.

Each memory controller provides five RDRAM channels that support PC800 Rambus inline memory modules (RIMMs). Four of the channels are used to provide memory, while the fifth is used to provide RAID-like redundancy.[7] Each channel is 16 bits wide, operates at 400 MHz and transfers data on both the rising and falling edges of the clock signal (double data rate) for a transfer rate of 800 MT/s, yielding 1.6 GB/s of bandwidth. The total memory bandwidth of the eight channels is 12.8 GB/s.

Cache coherence is provided by the memory controllers. Each memory controller has a cache coherence engine. The Alpha 21364 uses a directory cache coherence scheme where part of the memory is used to store Modified, Exclusive, Shared, Invalid (MESI) coherency data.

The R-box contains the network router. The network router connected the microprocessor to other microprocessors using four ports named North, South, East and West. Each port consisted of two 39-bit unidirectional links operating at 800 MHz. 32 bits were for data and 7 bits were for ECC. The network router also has a fifth port, used for I/O. This port connects to an IO7 application-specific integrated circuit (ASIC), which was a bridge to an AGP 4x channel and two PCI-X buses. The I/O port consisted of two unidirectional 32-bit links operating at 200 MHz, yielding a peak bandwidth of 3.2 GB/s. The I/O port link operated at a quarter of the clock frequency to simplify the design of the I/O ASIC.

The Alpha 21364 can connect to as many as 127 other microprocessors using two network topologies: shuffle and an 2D torus. The shuffle topology had more direct paths to other microprocessors, reducing latency and therefore improving performance, but was limited to connecting up to eight microprocessors as a result of its nature. The 2D torus topology enabled the network to feature up to 128 microprocessors.

In multiprocessing systems, each microprocessor is a node with its own memory. Accessing the memory of other nodes is possible, but with a latency. The latency increases with distance, thus the Alpha 21364 implements non-uniform memory access (NUMA) multiprocessing. I/O is also distributed in an identical fashion. An Alpha 21364 microprocessor in a multiprocessing system did not have to have its RIMM slots populated with memory or its I/O port populated with devices. It could use another microprocessor's memory and I/O.

The Alpha 21364 could operate in lock-step for fault-tolerant computers.[10] This feature was a result in Compaq's decision to migrate Tandem's Himalaya fault-tolerant servers from the MIPS architecture to Alpha. The machines however never used the microprocessor as the decision to phase out the Alpha in favor of the Itanium was made before the availability of the Alpha 21364.

The Alpha 21364 contained 152 million transistors. The die measured 21.1 mm by 18.8 mm for an area of 397 mm². It was fabricated by International Business Machines (IBM) in their 0.18 µm, seven-level copper complementary metal–oxide–semiconductor (CMOS) process. It was packaged in a 1,443-land flip-chip land grid array (LGA).[2] It used a 1.65 V power supply and a 1.5 V external interface for a maximum power dissipation of 155 W at 1.25 GHz.