DDR5 SDRAM

Unlike DDR4, all DDR5 chips have on-die ECC, where errors are detected and corrected before sending data to the CPU. This, however, is not the same as true ECC memory with extra data correction chips on the memory module. DDR5's on-die error correction is to improve reliability and to allow denser RAM chips which lowers the per-chip defect rate. There still exist non-ECC and ECC DDR5 DIMM variants; the ECC variants have extra data lines to the CPU to send error-detection data, letting the CPU detect and correct errors occurring in transit.[21]

Each DDR5 DIMM has two independent channels. Earlier DIMM generations featured only a single channel and one CA (Command/Address) bus controlling the whole memory module with its 64 (for non-ECC) or 72 (for ECC) data lines. Both subchannels on a DDR5 DIMM each have their own CA bus, controlling 32 bits for non-ECC memory and either 36 or 40 data lines for ECC memory, resulting in a total number of either 64, 72 or 80 data lines. The reduced bus width is compensated by a doubled minimum burst length of 16, which preserves the minimum access size of 64 bytes, which matches the cache line size used by modern x86 microprocessors.[22]

For use in personal computers and servers, multiple DDR5 memory chips are usually mounted on a circuit board to form memory modules, more commonly known as DIMMs. As with previous memory generations, there are multiple DIMM variants available for DDR5.

Unbuffered memory modules (UDIMMs) directly expose the memory chip interface to the module connector. Registered or load-reduced variants (RDIMMs/LRDIMMs) use additional active circuitry on the memory module in order to buffer the signals between the memory controller and the DRAM chips. This reduces the capacitive load on the DDR5 bus.

DDR5 RDIMMs/LRDIMMs use 12 V and UDIMMs use 5 V input. In order to prevent damage by accidental insertion of the wrong memory type, DDR5 UDIMMs and (L)RDIMMs are not mechanically compatible. Additionally, DDR5 DIMMs are supplied with management interface power at 3.3 V,[23][24] and use on-board circuitry (a power management integrated circuit[25] and associated passive components) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.

Standard DDR5 memory speeds range from 4000 to 6400 million transfers per second (PC5-32000 to PC5-51200).[3] Higher speeds may be added later, as happened with previous generations.

Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after eight transfers. The addressing range is also slightly extended as follows:

• The number of chip ID bits remains at three, allowing up to eight stacked chips.
• A third bank group bit (BG2) was added, allowing up to eight bank groups.
• The maximum number of banks per bank group remains at four.
• The number of row address bits remains at 17, for a maximum of 128K rows.
• One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips.
• The least-significant three column address bits (C0, C1, C2) are removed; all reads and writes must begin at a column address which is a multiple of eight.
• One bit is reserved for addressing expansion as either a fourth chip ID bit (CID3) or an additional row address bit (R17).

• Main Memory: DDR4 & DDR5 SDRAM / JEDEC
• DDR5 Full Spec Draft Rev0.1 – unfinished draft of the DDR5 standard