Opteron

Opteron combines two important capabilities in a single processor:

1. native execution of legacy x86 32-bit applications without speed penalties
2. native execution of x86-64 64-bit applications

The first capability is notable because at the time of Opteron's introduction, the only other 64-bit architecture marketed with 32-bit x86 compatibility (Intel's Itanium) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as major RISC architectures (such as SPARC, Alpha, PA-RISC, PowerPC, MIPS) have been 64-bit for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade path to 64-bit computing.

The Opteron processor possesses an integrated memory controller supporting DDR SDRAM, DDR2 SDRAM or DDR3 SDRAM (depending on processor generation). This both reduces the latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip.

In multi-processor systems (more than one Opteron on a single motherboard), the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel Xeon[2] which didn't have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a switched fabric, rather than a shared bus. In particular, the Opteron's integrated memory controller allows the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, contention for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for the Intel Core i7 family of processors and their Xeon derivatives.

Quad-core "Barcelona" Opteron

Six-core "Istanbul" Opteron

In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant dual-core; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver the performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost.

AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2 GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For multithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252.

Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and the 8000 Series (quad or octo socket-capable). The 1000 Series uses the AM2 socket. The 2000 Series and 8000 Series use Socket F.

AMD announced its third-generation quad-core Opteron chips on September 10, 2007[3][4] with hardware vendors announcing servers in the following month. Based on a core design codenamed Barcelona, new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips.[5] The fourth generation was announced in June 2009 with the Istanbul hexa-cores. It introduced HT Assist, an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated.[6]

In March 2010 AMD released the Magny-Cours Opteron 6100 series CPUs for Socket G34. These are 8- and 12-core multi-chip module CPUs consisting of two four or six-core dies with a HyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for the Istanbul CPUs to 3.20 GHz (6.40 GT/s).

AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications.

AMD released Socket 939 Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1 MB L2 cache (versus 512 KB for the Athlon 64) the Socket 939 Opterons are identical to the San Diego and Toledo core Athlon 64s, but are run at lower clock speeds than the cores are capable of, making them more stable.

Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike the majority of their Athlon 64 X2 cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224.

AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to the Agena Phenom X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest". The Socket AM2+ Opterons carry model numbers of 1352 (2.10 GHz), 1354 (2.20 GHz), and 1356 (2.30 GHz).

AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on a 45 nm manufacturing process and are similar to the Deneb-based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka". These CPUs carry model numbers of 1381 (2.50 GHz), 1385 (2.70 GHz), and 1389 (2.90 GHz).

Socket AM3+ was introduced in 2011 and is a modification of AM3 for the Bulldozer microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx.

Socket F (LGA 1207 contacts) is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. the "lidded land grid array" socket adds support for DDR2 SDRAM and improved HyperTransport version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with socket 1207 FX.

Socket G34 (LGA 1944 contacts) is one of the third generation of Opteron sockets, along with Socket C32. This socket supports Magny-Cours Opteron 6100, Bulldozer-based Interlagos Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of DDR3 SDRAM (two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to the traditional registered ECC RAM.

Socket C32 (LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar to Socket F but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM.

The Opteron line saw an update with the implementation of the AMD K10 microarchitecture. New processors, launched in the third quarter of 2007 (codename Barcelona), incorporate a variety of improvements, particularly in memory prefetching, speculative loads, SIMD execution and branch prediction, yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.[7]

In 2007 AMD introduced a scheme to characterize the power consumption of new processors under "average" daily usage, named average CPU power (ACP).

The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or Socket FT3.[8]

APU features table

• CPU steppings: B3, C0, CG
• L1 cache: 64 + 64 KB (data + instructions)
• L2 cache: 1024 KB, full speed
• MMX, Extended 3DNow!, SSE, SSE2, AMD64
• Socket 940, 800 MHz HyperTransport
• Registered DDR SDRAM required, ECC possible
• VCore: 1.50–1.55 V
• Max power (TDP): 89 W
• First release: April 22, 2003[9]
• Clock rate: 1.4–2.4 GHz (x40 – x50)

• CPU steppings: E4
• L1 cache: 64 + 64 KB (data + instructions)
• L2 cache: 1024 KB, full speed
• MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
• Socket 940, 800 MHz HyperTransport
• Socket 939/Socket 940, 1000 MHz HyperTransport
• Registered DDR SDRAM required for socket 940, ECC possible
• VCore: 1.35–1.4 V
• Max power (TDP): 95 W
• NX bit
• 64-bit segment limit checks for VMware-style binary-translation virtualization.
• Optimized Power Management (OPM)
• First release: December 2004
• Clock rate: 1.6–3.0 GHz (x42 – x56)

• CPU steppings: E1, E6
• First release: April 2005
• Clock rate: 1.6–2.8 GHz (x60, x65, x70, x75, x80, x85, x90)
• Socket 939/Socket 940, 1000 MHz HyperTransport
• NX bit

• CPU steppings: F2, F3
• L1 cache: 64 + 64 KB (data + instructions)
• L2 cache: 2 × 1024 KB, full speed
• MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
• Socket F, 1000 MHz HyperTransport – Opteron 22yy, 82yy
• Socket AM2, 1000 MHz HyperTransport – Opteron 12yy
• VCore: 1.35 V
• Max power (TDP): 95 W
• NX bit
• AMD-V Virtualization
• Optimized Power Management (OPM)
• First release: ?????? 2006
• Clock rate: 1.8–3.2 GHz (xx10, xx12, xx14, xx16, xx18, xx20, xx22, xx24)

• CPU steppings: BA, B3
• L1 cache: 64 + 64 KB (data + instructions) per core
• L2 cache: 512 KB, full speed per core
• L3 cache: 2048 KB, shared
• MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, SSE4a, ABM
• Socket F, Socket AM2+, HyperTransport 3.0 (1.6–2 GHz)
• Registered DDR2 SDRAM required, ECC possible
• VCore: 1.2 V
• Max power (TDP): 95 W
• NX bit
• 2nd-generation AMD-V Virtualization with Rapid Virtualization Indexing (RVI)
• Split power plane dynamic power management
• First release: September 10, 2007
• Clock rate: 1.7–2.5 GHz

• CPU steppings: C2
• L3 cache: 6 MB, shared
• Clock rate: 2.3–2.9 GHz
• HyperTransport 1.0, 3.0
• 20% reduction in idle power consumption[10]
• support for DDR2 800 MHz memory (Socket F)[11]
• support for DDR3 1333 MHz memory (Socket AM3)

Released June 1, 2009.

• CPU steppings: D0
• L3 cache: 6 MB, shared
• Clock rate: 2.2–2.8 GHz
• HyperTransport 3.0
• HT Assist
• Support for DDR2 800 MHz memory [11]

Released March 29, 2010.

• CPU steppings: D1
• Multi-chip module consisting of two quad-core dies
• L2 cache: 8 × 512 KB
• L3 cache: 2 × 6 MB, shared
• Clockrate: 2.0–2.6 GHz
• Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1333 MHz memory
• Socket G34

Released March 29, 2010

• CPU steppings: D1
• Multi-chip module consisting of two hexa-core dies
• L2 cache, 12 × 512 KB
• L3 cache: 2 × 6 MB, shared
• Clock rate: 1.7–2.5 GHz
• Four HyperTransport 3.1 links at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1333 MHz memory
• Socket G34

Released June 23, 2010

• CPU steppings: D0
• L3 cache: 6 MB
• Clock rate: 2.2 GHz (4122), 2.6 GHz (4130)
• Two HyperTransport links at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3-1333 memory
• Socket C32

Released June 23, 2010

• CPU steppings: D1
• L3 cache: 6 MB
• Clock rate: 1.7–2.8 GHz
• Two HyperTransport links at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3-1333 memory
• Socket C32

Released March 20, 2012.

• CPU steppings: B2
• Single processor Bulldozer module
• L2 cache: 2 × 2 MB
• L3 cache: 4 MB
• Clock rate: 2.5 GHz (3250) – 2.7 GHz (3260)
• HyperTransport 3 (5.2 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, up to 3.5 GHz (3250), up to 3.7 GHz (3260)
• Supports uniprocessor configurations only
• Socket AM3+

Released March 20, 2012.

• CPU steppings: B2
• Single processor Bulldozer module
• L2 cache: 4 × 2 MB
• L3 cache: 8 MB
• Clock rate: 2.4 GHz
• HyperTransport 3 (5.2 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, up to 3.5 GHz
• Supports uniprocessor configurations only
• Socket AM3+

Released November 14, 2011.

• CPU steppings: B2
• Single die consisting of three dual-core Bulldozer modules
• L2 cache: 6 MB
• L3 cache: 8 MB, shared
• Clock rate: 2.7–3.3 GHz (up to 3.1–3.7 GHz with Turbo CORE)
• Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support
• Supports up to dual-processor configurations
• Socket C32

Released November 14, 2011.

• CPU steppings: B2
• Single die consisting of four dual-core Bulldozer modules
• L2 cache: 8 MB
• L3 cache: 8 MB, shared
• Clockrate: 1.6–3.0 GHz (up to 3.0-3.7 GHz with Turbo CORE)
• Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support
• Supports up to dual-processor configurations
• Socket C32

Released November 14, 2011.

• CPU steppings: B2
• Multi-chip module consisting of two dies, each with one dual-core Bulldozer module
• L2 cache: 2 × 2 MB
• L3 cache: 2 × 8 MB, shared
• Clockrate: 3.3 GHz
• HyperTransport 3 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Does not support Turbo CORE
• Supports up to quad-processor configurations
• Socket G34

Released November 14, 2011.

• CPU steppings: B2
• Multi-chip module consisting of two dies, each with two dual-core Bulldozer modules
• L2 cache: 2 × 4 MB
• L3 cache: 2 × 8 MB, shared
• Clockrate: 2.6, 3.0 GHz (up to 3.2 and 3.6 GHz with Turbo CORE)
• Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support
• Supports up to quad-processor configurations
• Socket G34

Released November 14, 2011.

• CPU steppings: B2
• Multi-chip module consisting of two dies, each with three dual-core Bulldozer modules
• L2 cache: 2 × 6 MB
• L3 cache: 2 × 8 MB, shared
• Clock rate: 2.4, 2.6 GHz (up to 3.1 and 3.3 GHz with Turbo CORE)
• Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support
• Supports up to quad-processor configurations
• Socket G34

Released November 14, 2011.

• CPU steppings: B2
• Multi-chip module consisting of two dies, each with four dual-core Bulldozer modules
• L2 cache: 2 × 8 MB
• L3 cache: 2 × 8 MB, shared
• Clock rate: 1.6–2.7 GHz (up to 2.9-3.5 GHz with Turbo CORE)
• Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support
• Supports up to quad-processor configurations
• Socket G34

Released December 4, 2012.

• CPU steppings: C0
• Single die consisting of two Piledriver modules
• L2 cache: 2 × 2 MB
• L3 cache: 8 MB, shared
• Clockrate: 1.9 GHz (3320 EE) – 2.8 GHz (3350 HE)
• 1 × HyperTransport 3 (5.2 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, up to 2.5 GHz (3320 EE), up to 3.8 GHz (3350 HE)
• Supports uniprocessor configurations only
• Socket AM3+

Released December 4, 2012.

• CPU steppings: C0
• Single die consisting of four Piledriver modules
• L2 cache: 4 × 2 MB
• L3 cache: 8 MB, shared
• Clock rate: 2.6 GHz
• 1 × HyperTransport 3 (5.2 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, pp to 3.6 GHz
• Supports uniprocessor configurations only
• Socket AM3+

Released December 4, 2012

• CPU steppings: C0
• Single die consisting of two Piledriver modules
• L2 cache: 2 × 2 MB
• L3 cache: 8 MB, shared
• Clock rate: 2.2 GHz
• 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, up to 3.0 GHz
• Supports up to dual-processor configurations
• Socket C32

Released December 4, 2012

• CPU steppings: C0
• Single die consisting of three Piledriver modules
• L2 cache: 3 × 2 MB
• L3 cache: 8 MB, shared
• Clockrate: 3.0 GHz (4332 HE) – 3.5 GHz (4340)
• 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, from 3.5 GHz (4334) to 3.8 GHz (4340)
• Supports up to dual-processor configurations
• Socket C32

Released December 4, 2012

• CPU steppings: C0
• Single die consisting of four Piledriver modules
• L2 cache: 4 × 2 MB
• L3 cache: 8 MB, shared
• Clock rate: 2.6 GHz (4376 HE) – 3.1 GHz (4386)
• 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, from 3.6 GHz (4376 HE) to 3.8 GHz (4386)
• Supports up to dual-processor configurations
• Socket C32

Released November 5, 2012.

• CPU steppings: C0
• Multi-chip module consisting of two dies, each with one Piledriver module
• L2 cache: 2 MB per die (4 MB total)
• L3 cache: 2 × 8 MB, shared within each die
• Clock rate: 3.5 GHz
• 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Does not support Turbo CORE
• Supports up to quad-processor configurations
• Socket G34

Released November 5, 2012.

• CPU steppings: C0
• Multi-chip module consisting of two dies, each with two Piledriver module
• L2 cache: 2 × 2 MB per die (8 MB total)
• L2 cache: 2 × 8 MB, shared within each die
• Clock rate: 2.8 GHz (6320) – 3.2 GHz (6328)
• 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, from 3.3 GHz (6320) to 3.8 GHz (6328)
• Supports up to quad-processor configurations
• Socket G34

Released November 5, 2012.

• CPU steppings: C0
• Multi-chip module consisting of two dies, each with three Piledriver module
• L2 cache: 3 × 2 MB per die (12 MB total)
• L3 cache: 2 × 8 MB, shared within each die
• Clock rate: 2.6 GHz (6344) – 2.8 GHz (6348)
• 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, from 3.2 GHz (6344) to 3.4 GHz (6348)
• Supports up to quad-processor configurations
• Socket G34

Released November 5, 2012.

• CPU steppings: C0
• Multi-chip module consisting of two dies, each with four Piledriver module
• L2 cache: 4 × 2 MB per die (16 MB total)
• L3 cache: 2 × 8 MB, shared within each die
• Clock rate: 1.8 GHz (6366 HE) – 2.8 GHz (6386 SE)
• 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
• HT Assist
• Support for DDR3 1866 MHz memory
• Turbo CORE support, from 3.1 GHz (6366 HE) to 3.5 GHz (6386 SE)
• Supports up to quad-processor configurations
• Socket G34

Released May 29, 2013

• Single SoC with one Jaguar module and integrated I/O
• Configurable CPU frequency and TDP
• L2 cache: 2 MB shared
• CPU frequency: 1.0–2.0 GHz
• Max. TDP: 9–17 W
• Support for DDR3-1600 memory
• Socket FT3

Released May 29, 2013

• Single SoC with one Jaguar module, integrated GCN GPU and I/O
• Configurable CPU/GPU frequency and TDP
• L2 cache: 2 MB shared
• CPU frequency: 1.1–1.9 GHz
• GPU frequency: 266–600 MHz
• GPU cores: 128
• Max. TDP: 11–22 W
• Support for DDR3-1600 memory
• Socket FT3

The Opteron A1100-series "Seattle" (28 nm) are SoCs based on ARM Cortex-A57 cores that use the ARMv8-A instruction set. They were first released in January 2016.[12][13]

• Cores: 4–8
• Frequency: 1.7–2.0 GHz
• L2 cache: 2 MB (4 core) or 4 MB (8 core)
• L3 cache: 8 MB
• Thermal design power: 25 W (4 core) or 32 W (8 core)
• Up to 64 GB DDR3L-1600 and up to 128 GB DDR4-1866 with ECC
• SoC peripherals include 14 × SATA 3, 2 × integrated 10 GbE LAN, and eight PCI Express lanes in ×8, ×4, and ×2 configurations

Released June, 2017

• L2 cache: 1 MB
• CPU frequency: 1.6 GHz
• Turbo CORE support, 3.0 GHz
• GPU frequency: 800 MHz
• TDP: 12–15 W
• Support for DDR4 1600 MHz memory

• L2 cache: 2 × 1 MB
• CPU frequency: 1.8–2.1 GHz
• Turbo CORE support, 3.2–3.4 GHz
• GPU frequency: 800 MHz
• TDP: 12–35 W
• Support for DDR4 2400 MHz memory

AMD released some Opteron processors without Optimized Power Management (OPM) support, which use DDR memory. The following table describes those processors without OPM.

AMD recalled some E4 stepping-revision single-core Opteron processors, including ×52 (2.6 GHz) and ×54 (2.8 GHz) models which use DDR memory. The following table describes affected processors, as listed in AMD Opteron ×52 and ×54 Production Notice of 2006.[16]

The affected processors may produce inconsistent results if three specific conditions occur simultaneously:

• The execution of floating point-intensive code sequences
• Elevated processor temperatures
• Elevated ambient temperatures

A software verification tool for identifying the AMD Opteron processors listed in the above table that may be affected under these specific conditions is available, only to AMD OEM partners. AMD will replace those processors at no charge.