Hitachi SR2201

The Hitachi SR2201 was a distributed memory parallel system that was introduced in March 1996 by Hitachi. Its processor, the 150 MHz HARP-1E based on the PA-RISC 1.1 architecture, solved the cache miss penalty by pseudo vector processing (PVP). In PVP, data was loaded by prefetching to a special register bank, bypassing the cache. Each processor had a peak performance of 300 MFLOPS, giving the SR2201 a peak performance of 600 GFLOPS. Up to 2048 RISC processors could be connected via a high-speed three-dimensional crossbar network, which was able to transfer data at 300 MB/s over each link.

In February 1996, two 1024-node systems were installed at the University of Tokyo and the University of Tsukuba. The latter was extended to the non-commercial CP-PACS system. An upgrade to a 2048-node system, which reached a peak speed of 614 GFLOPS, was completed at the end of September 1996. The CP-PACS was run by the Center for Computational Physics, formed for that purpose. The 1024 processor system of the SR2201 achieved 220.4 GFLOPS on the LINPACK benchmark, which corresponded to 72% of the peak performance.[1][2][3]

References
  1. H. Fujii, Y. Yasuda, H. Akashi, Y. Inagami, M. Koga, O. Ishihara, M. Kashiyama, H. Wada, T. Sumimoto, Architecture and performance of the Hitachi SR2201 massively parallel processor system, Proceedings of 11th International Parallel Processing Symposium, April 1997, Pages 233-241.
  2. Y. Iwasaki, The CP-PACS project, Nuclear Physics B - Proceedings Supplements, Volume 60, Issues 1-2, January 1998, pp. 246–254.
  3. A. J. van der Steen, Overview of recent supercomputers, Publication of the NCF, Stichting Nationale Computer Faciliteiten, the Netherlands, January 1997.
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