p–n junction isolation

p–n junction isolation is a method used to electrically isolate electronic components, such as transistors, on an integrated circuit (IC) by surrounding the components with reverse biased p–n junctions.

Introduction

By surrounding a transistor, resistor, capacitor or other component on an IC with semiconductor material which is doped using an opposite species of the substrate dopant, and connecting this surrounding material to a voltage which reverse-biases the p–n junction that forms, it is possible to create a region which forms an electrically isolated "well" around the component.

Operation

Assume that the semiconductor wafer is p-type material. Also assume a ring of n-type material is placed around a transistor, and placed beneath the transistor. If the p-type material within the n-type ring is now connected to the negative terminal of the power supply and the n-type ring is connected to the positive terminal, the 'holes' in the p-type region are pulled away from the p–n junction, causing the width of the nonconducting depletion region to increase. Similarly, because the n-type region is connected to the positive terminal, the electrons will also be pulled away from the junction.

This effectively increases the potential barrier and greatly increases the electrical resistance against the flow of charge carriers. For this reason there will be no (or minimal) electric current across the junction.

At the middle of the junction of the p–n material, a depletion region is created to stand-off the reverse voltage. The width of the depletion region grows larger with higher voltage. The electric field grows as the reverse voltage increases. When the electric field increases beyond a critical level, the junction breaks down and current begins to flow by avalanche breakdown. Therefore, care must be taken that circuit voltages do not exceed the breakdown voltage or electrical isolation ceases.

History

In an article entitled "Microelectronics", published in Scientific American, September 1977 Volume 23, Number 3, pp. 63–9, Robert Noyce wrote:

"The integrated circuit, as we conceived and developed it at Fairchild Semiconductor in 1959, accomplishes the separation and interconnection of transistors and other circuit elements electrically rather than physically. The separation is accomplished by introducing pn diodes, or rectifiers, which allow current to flow in only one direction. The technique was patented by Kurt Lehovec at the Sprague Electric Company".

Sprague Electric Company engineer Kurt Lehovec filed U.S. Patent 3,029,366 for p–n junction isolation in 1959, and was granted the patent in 1962. He is reported (during his lectures on semiconductor memory cells) to have said "I never got a dime out of it [the patent]." However, I T History states he was paid (pro forma) at least one dollar for what is possibly the most important invention in history, as it also was instrumental in the invention of the LED and the solar cell, both of which Lau Wai Shing says Lehovec also pioneered the research of.

When Robert Noyce invented the monolithic integrated circuit in 1959, his idea of p–n junction isolation was based on Hoerni's planar process.[1] In 1976, Noyce stated that, in January 1959, he did not know about the work of Lehovec.[2]

See also

References
  1. Brock, D.; Lécuyer, C. (2010). Lécuyer, C. (ed.). Makers of the Microchip: A Documentary History of Fairchild Semiconductor. MIT Press. p. 158. ISBN 9780262014243.
  2. "Interview with Robert Noyce, 1975–1976". IEEE. Archived from the original on 2012-09-26. Retrieved 2012-04-22.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.