Front end of line

The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in the semiconductor.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.[2]

BEOL (metalization layer) and FEOL (devices).
CMOS fabrication process

For the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:[3]

  1. Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafer.
  2. Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm)
  3. Well formation
  4. Gate module formation
  5. Source and drain module formation

See also

References
  1. Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.
  2. "FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd". USJC：United Semiconductor Japan Co., Ltd. | 三重県桑名市の300mm半導体ウェーハ工場を製造拠点にしたファウンドリ専業メーカーです。超低消費電力、不揮発メモリなど先進テクノロジーを世界中のお客様に提供しています。 (in Japanese). 2019-02-22. Retrieved 2022-09-27.
  3. Ramsundar, Bharath. "A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics". deepforest.substack.com. Retrieved 2022-09-27.

Further reading
  • "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)


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