DEC 7000 AXP and DEC 10000 AXP

The Model 600 systems used the KN7AA CPU module, which contained either a 182 MHz DECchip 21064 (EV4) or 200 MHz DECchip 21064 (EV4S) microprocessor. The 182 MHz version was only used in DEC 7000 AXP, with the 200 MHz version used in the DEC 10000 AXP at first, and later in the DEC 7000 AXP. The Model 700 systems used the KN7AB CPU module containing a 275 MHz DECchip 21064A (EV45).

Other than the differences in the microprocessor used and their clock frequencies, all CPU modules also featured 4 MB of B-cache (L2 cache) and two LEVI gate arrays for interfacing the module to the LSB bus. The B-cache size of 4 MB was chosen as it was the largest size achievable with 4-bit SRAMs containing 262,144 words (128 KB) on a 128-bit system bus. The B-cache SRAMs and drivers reside on both sides of the CPU module.

The LEVI also implement the Gbus, an 8-bit bus to which hardware providing console functionality is connected to. Devices connected to the Gbus are a set of seven 128 KB (8-bit by 131,072-word) flash ROMs for storing the console program, an 8 KB (8-bit by 8,192-entry) EEPROM for storing miscellaneous parameter and log information, three devices containing two UARTs each for implementing six serial lines and a watch chip containing a time-of-year clock, 50 bytes of battery-backed-up RAM and a lithium battery rated to last for 10 years.

The DEC 7000 AXP and DEC 10000 AXP supported two types of memory module, the MS7AA and the MS7BB, which differ in function. The MS7AA provided dynamic random access memory (DRAM) for implementing the main memory, whereas the MS7BB provided a non-volatile cache for accelerating Network File System (NFS) performance when used in conjunction with Prestoserve software from Legato Systems.

The MS7AA memory module has capacities of 64 MB, 128 MB, 256 MB, 512 MB and 2 GB. The module and its components are clocked at 50 MHz. The MIC (Memory Interface Controller), provides the interface to the LSB bus, and is made up of two gate arrays, MIC-A and MIC-B. The two gate arrays both provide a 64-bit data path, which when combined results in a 128-bit data path that matches the width of the LSB bus. The two gate arrays, while similar, are not identical. MIC-A also serves as the memory controller, interfaces to the LSB bus' control lines and coordinates the operation of MIC-B, which provides the module with SECDED ECC capability.

Also on the module are 18 MDC (Memory Data Controller) chips. The purpose of the MDCs is to act as a buffer between the 512-bit memory bus and the 128-bit LSB bus. During memory read operations, the MDCs buffer a 512-bit transaction from the memory and forwards it to the MIC in four 128-bit transactions over four 20 nanosecond cycles. Memory write operations are similar, but with the roles reversed. The MDCs instead accumulate four 128-bit transactions from the MIC over four 20 nanosecond cycles before writing to the memory in one 512-bit transaction.

The memory is implemented with 512 KB or 2 MB DRAM chips and organised into one to eight "strings", the smallest group of DRAMs required to fill the width of a 64-byte LSB bus transaction. Each string consists of 144 DRAM chips. Depending on the module's capacity, the DRAM chips are either surface mounted on both sides of the board or mounted on SIMMs that are soldered onto the board. The SIMMs are not socketed as Digital's engineers found the arrangement to be unreliable.

The modules and the memory subsystem of the DEC 7000/1000 supports interleaving. Modules with more than two strings supports two-way interleaving. At a system level, the memory subsystem supports a maximum of eight-way interleaving. If the configuration results in more levels of interleaving than the memory subsystem can support, multiple memory modules are then grouped into larger banks so the level of interleaving in the memory subsystem does not exceed the maximum of eight ways.

The MS7BB memory module was a NFS accelerator. It contained 16 MB of non-volatile memory used to cache writes to the file system. The non-volatile memory was built from SRAM, and in event of power failure, a battery pack containing 14 batteries located on the module would power the SRAM for up to 48 hours, retaining the data.

The I/O port module provides the means to implement I/O buses. It contains four parallel ports (not to be confused with the parallel ports found in personal computers) that connect to adapters, which implement an expansion bus, in the plug-in units (PIUs) housed in the system cabinet or expander cabinet via cables that are up to three meters long. An I/O controller gate array on the module interfaces the parallel ports to the LSB bus by serving as a bridge, receiving a transaction from a bus and passing it on to another. The I/O controller has 256 MB/s of bandwidth that the four parallel ports share. Each parallel port, if sending data from the memory to the I/O subsystem, has a maximum bandwidth of 88 MB/s. If the parallel port is sending data from the I/O subsystem to the memory, it has a maximum bandwidth of 135 MB/s.

Plug-in units (PIUs) are modular enclosures that house options. The DEC 7000/10000 AXP supported PIUs implementing the Futurebus+ Profile B and XMI, PIUs housing SCSI and DSSI drives, and a PIU housing batteries.

Futurebus expansion capability was provided by the DWLAA PIU. It contains a card cage with nine usable slots and the DWLAA adapter, which implements the bus and interfaces it to the I/O controller on the I/O port module. The Futurebus PIU can be installed in PIU quadrants 2 and 4 and. Futurebus capability was optional and up to three can be installed in a system, with a maximum of two per cabinet. Futurebus capability required the system to have a XMI bus.

XMI expansion capability was provided by the DWLMA PIU. It contains a card cage with 14 slots, with 12 of those slots usable by adapters. Two slots are unusable as they are reserved by the control and interface modules, the DWLMA module, which implements the XMI bus and interfaces it to the I/O controller on the I/O port module, and clock and arbitration module, which provides the XMI clock. The XMI PIU requires two PIU quadrants as they are twice as deep as the other PIUs, and can be installed only in the bottom left or right PIU quadrants. One to four XMI PIUs are supported in a system, with a maximum of two per any type of cabinet.

SCSI devices are housed in the BA655 PIU, which contains two modular expansion shelves placed side by side. The left shelf can house seven 3.5-inch (89 mm) drives and the right shelf can house two 5.25-inch (133 mm) drives. The system cabinet can have up to two SCSI PIUs and expander cabinet up to four. DSSI devices are housed in the BA654 PIU which contains three Storage Array Building Blocks (SBBs), each housing two 5.25-inch (133 mm) drives. The system cabinet can have up to two DSSI PIUs and the expander cabinet up to six.

The SCSI and DSSI PIUs did not contain hardware that provides the SCSI or DSSI bus to which the drives connect to. Instead, they are connected to a KZMSA-AB adapter for SCSI, or a KFMSB adapter for DSSI, which is installed in the XMI PIU. The KZMSA-AB adapter provides two 8-bit single-ended SCSI-2 buses (or differential 8-bit SCSI-2 buses if DWZZA bus converters are used) that support seven drives each, while the KFMSB adapter provides two DSSI buses. Unlike the Futurebus and XMI PIUs, the SCSI and DSSI PIUs can be installed in any PIU quadrant.